Display device

ABSTRACT

A display device includes a plurality of first pixels, a plurality of second pixels, a plurality of first multiplexers, a plurality of second multiplexers, a plurality of first traces, a plurality of second traces, and an integrated circuit. First multiplexers are used to control first pixels. Second multiplexers are used to control second pixels. First traces are coupled to each of first multiplexers. Second traces are coupled to each of second multiplexers. Integrated circuit includes at least two first polarity pins s and at least two second polarity pins. At least two first polarity pins s are adjacent. At least two second polarity pins are adjacent. At least two first polarity pins and at least two second polarity pins are arranged alternately. At least two first polarity pins s are coupled to first traces. At least two second polarity pins are coupled to second traces.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Taiwan Application Serial Number109135556, filed on Oct. 14, 2020, which is herein incorporated byreference in its entirety.

BACKGROUND Field of Invention

The present disclosure relates to an electronic device. Moreparticularly, the present disclosure relates to a display device.

Description of Related Art

In recent years, due to needs of narrow border of a panel, many displaydevices are gradually using in a Chip On Film (COF) technology such thata height of a fan-out area in narrow border of a panel is compressed.Furthermore, a power consumption of a fan-out area accounts for a largeproportion of a power consumption of a total panel.

For the foregoing reason, there is a need to provide structures of adisplay device or a display panel to solve the problems of the priorart.

SUMMARY

One aspect of the present disclosure provides a display device. Thedisplay device includes a plurality of first pixels, a plurality ofsecond pixels, a plurality of first multiplexers, a plurality of secondmultiplexers, a plurality of first traces, a plurality of second traces,and an integrated circuit. The first pixels and the second pixels arearranged in an interlaced manner. The first multiplexers are configuredto control the first pixels, and include at least three first switches.One of the at least three first switches is configured to control thesecond pixels. The second multiplexers are configured to control thesecond pixels, and include at least three second switches. One of the atleast three second switches is configured to control the first pixels.Each of the first multiplexers and each of the second multiplexers arearranged in an interlaced manner. The first traces are coupled to eachof the first multiplexers. The second traces are coupled to each of thesecond multiplexers. The integrated circuit includes at least two firstpolarity pins and at least two second polarity pins. The at least twofirst polarity pins are adjacent. The at least two second polarity pinsare adjacent. The at least two first polarity pins and the at least twosecond polarity pins are arranged in an interlaced manner. The at leasttwo first polarity pins are coupled to the first traces. The at leasttwo second polarity pins are coupled to the second traces. A polarity ofeach of the first polarity pins is opposite to a polarity of each of thesecond polarity pins.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure can be more fully understood by reading thefollowing detailed description of the embodiment, with reference made tothe accompanying drawings as follows:

FIG. 1 depicts a part structure diagram of a display device according tosome embodiments of the present disclosure;

FIG. 2 depicts an enlarged view of a part structure diagram of a displaydevice according to some embodiments of the present disclosure;

FIG. 3 depicts a sectional view of a fan-out area of a display deviceaccording to some embodiments of the present disclosure;

FIG. 4 depicts an enlarged view of a part structure diagram of a displaydevice according to some embodiments of the present disclosure; and

FIG. 5 depicts an enlarged view of a part structure diagram of a displaydevice according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

Reference will now be made in detail to the present embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or like parts.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting of thepresent disclosure. As used herein, the singular forms “a,” “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise.

Furthermore, it should be understood that the terms, “comprising”,“including”, “having”, “containing”, “involving” and the like, usedherein are open-ended, that is, including but not limited to.

The terms used in this specification and claims, unless otherwisestated, generally have their ordinary meanings in the art, within thecontext of the disclosure, and in the specific context where each termis used. Certain terms that are used to describe the disclosure arediscussed below, or elsewhere in the specification, to provideadditional guidance to the practitioner skilled in the art regarding thedescription of the disclosure.

FIG. 1 depicts a part structure diagram of a display device 100according to some embodiments of the present disclosure. In someembodiments, as shown in FIG. 1, the display device 100 includes a panel110, a multiplexer area A13, a flexible printed circuit 120, and anintegrated circuit 130. Multiplexers in the multiplexer area A13 arelocated on the panel 110. The integrated circuit 130 is located on theon the 120.

In addition, as shown in FIG. 1, the panel 110 includes a display area Dand a peripheral area A1. The display area D is located at a first sideof the panel 110. The peripheral area A1 is located at a second side ofthe panel 110. The first side is opposite to the second side. Althoughthe first side and second side are shown as an upper side and a lowerside in the figure. In practice, the first side and second side are notlimited to the upper side and the lower side.

In some embodiments, the display area D includes a plurality of firstpixels (not shown in the figure) and a plurality of second pixels (notshown in the figure), In order to facilitate the understanding ofstructures of a display device, detail structures will be explained inthe following paragraphs.

In some embodiments, the multiplexer area A13 is located in theperipheral area A1. In some embodiments, the flexible printed circuit120 includes a package fan-out area A2.

In some embodiments, the integrated circuit 130 is attached to theflexible printed circuit 120 through Chip on film (COF) technology, andis partly overlapped to form a bonding area A11 with the flexibleprinted circuit 120. In some embodiments, the bonding area A11 islocated in the peripheral area A1.

FIG. 2 depicts an enlarged view of a part structure diagram of a displaydevice 100 according to some embodiments of the present disclosure. Insome embodiments, FIG. 2 is an enlarged view corresponding to theperipheral area A1 shown in FIG. 1. In some embodiments, the peripheralarea A1 includes the bonding area A11, a fan-out area A12, themultiplexer area A13, and a data line area A14.

In some embodiments, please refer to FIG. 2, the display device 100includes a plurality of first pixels (ex. a first pixel P11 and a firstpixel P12), a plurality of second pixels (ex. a second pixel P21 and asecond pixel P22), a plurality of first multiplexers (ex. a firstmultiplexer M11 and a first multiplexer M12), a plurality of secondmultiplexers (ex. a second multiplexer M21 and a second multiplexerM22), a plurality of first traces T1, and a plurality of second tracesT2. The first pixels and the second pixels are arranged in an interlacedmanner. Each of pixels includes three sub pixels. The three sub pixelsare configured to display red, green, blue, and other colorsrespectively. Each of sub-pixels is connected to the corresponding dataline respectively. It should be noted that the first pixels and thesecond pixels shown in the figure represent pixels controlled by theadjacent multiplexers in different rows.

In some embodiments, the data line area A14 is a narrow area which thedata lines leave from multiplexer area A13 and enter before the displayarea D shown in FIG. 1. The data lines are configured to the pixels andthe multiplexers. In other words, each of the multiplexers is configuredto connect to the pins so as to receive signals from the integratedcircuit 130, and is configured to connect to the corresponding datalines and the corresponding sub pixels.

In addition, please refer to FIG. 2, the multiplexer area A13 includes aplurality of first multiplexers (ex. a first multiplexer M11 and a firstmultiplexer M12) and a plurality of second multiplexers (ex. a secondmultiplexer M21 and second multiplexer M22). The first multiplexers areconfigured to control the first pixels (ex. the first pixel P11 and thefirst pixel P12). Each of the first multiplexers includes at least threefirst switches (ex. a first switch Z1, a first switch Z2, and a firstswitch Z3). One of the at least three first switches (ex. the firstswitch Z2) is configured to control the second pixels (ex. the secondpixel P21). The second multiplexers are configured to control the secondpixels. Each of the second multiplexers includes at least three secondswitches (ex. a second switch Z4, a second switch Z5, and a secondswitch Z6). One of the at least three second switches (ex. the secondswitch Z5) is configured to control the first pixels (ex. the firstpixel P11). Each of the first multiplexers and each of the secondmultiplexers are arranged in an interlaced manner.

Further, the fan-out area A12 includes the first traces T1 and thesecond traces T2. The first traces T1 are coupled to each of the firstmultiplexers (ex. the first multiplexer M11 and the first multiplexerM12). The second traces T2 are coupled to each of the secondmultiplexers (ex. the second multiplexer M21 and the second multiplexerM22).

In addition, the bonding area A11 includes at least two first polaritypins S1 and at least two second polarity pins S2. The at least two firstpolarity pins S1 are adjacent. The at least two second polarity pins S2are adjacent. The at least two first polarity pins S1 and the at leasttwo second polarity pins S2 are arranged in an interlaced manner. The atleast two first polarity pins S1 are coupled to the first traces T1. Theat least two second polarity pins S2 are coupled to the second tracesT2. For example, a first polarity pin S11 and First polarity pin S12 areadjacent. A second polarity pin S21 and second polarity pin S22 areadjacent. A polarity of each of the first polarity pins is opposite to apolarity of each of the second polarity pins.

In some embodiments, in order to facilitate the understanding of asectional view of structures of the fan-out area A12 of the displaydevice 100 of present disclosure, please refer to FIG. 2 and FIG. 3,FIG. 3 depicts a sectional view of a fan-out area A12 of a displaydevice 100 according to some embodiments of the present disclosure. Thesectional view of the fan-out area A12 shown in FIG. 3 is correspondingto the fan-out area A12 shown in FIG. 2. The first traces T1 and thesecond traces T2 in the fan-out area A12 include different structures ofa front section A121, a middle section A122, and a rear section A123from the bottom to top of the figure, but not limited to the embodimentsshown in the figure and narrative sequence in these embodiments.

In some embodiments, each of the first traces which are coupled to theat least two first polarity pins is adjacent. Each of the second traceswhich are coupled to the at least two second polarity pins is adjacent.It should be noted that the structure in this embodiment is a changestructure of the front section A121 of the fan-out area A12. Forexample, please refer to FIG. 2, the first polarity pin S11 is coupledto the first trace T11. The first polarity pin S12 is coupled to thefirst trace T12. The first trace T11 and the first trace T12 areadjacent. Similarly, the second polarity pin S21 is coupled to thesecond trace T21. The second polarity pin S22 is coupled to the secondtrace T22. The second trace T21 and the second trace T22 are adjacent.It should be noted that the first traces T1 and the second traces T2 areadjacent in the front section A121 of the fan-out area A12 which thetraces are just out of the bonding area A11.

In some embodiments, please refer to FIG. 2 and FIG. 3, the sectionalstructures of the fan-out area A12 include a first conductive layer F1and a second conductive layer F2. The second conductive layer F2 islocated on the upper layer of the first conductive layer F1. The secondconductive layer F2 and the first conductive layer F1 are electricallyinsulated from each other. The first trace T11 and the first trace T12of the first traces which are adjacent are disposed on the firstconductive layer F1 and the second conductive layer F2, and areoverlapped to each other in a vertical projection direction. Theadjacent second trace T21 and the second trace T22 of the second tracesare disposed on the first conductive layer F1 and the second conductivelayer F2, and are overlapped to each other in a vertical projectiondirection. It should be noted that the fan-out area A12 is composed ofmultiple layers of metal. Each of the first traces T1 is disposed on thedifferent layers respectively. Each of the second traces T2 is disposedon the different layers respectively. Further, the structure in thisembodiment is a change structure of the middle section A122 of thefan-out area A12. If the fan-out area A12 is located on a XY-plane, thefirst conductive layer F1 and the second conductive layer F2 extendalong a Z-axis. For example, the first trace T11 is disposed on thefirst conductive layer F1, and the first trace T12 is disposed on thesecond conductive layer F2. The first trace T11 and the first trace T12are overlapped to each other a vertical projection direction. Similarly,the second trace T21 and the second trace T22 are disposed on thedifferent conductive layers, and are overlapped to each other a verticalprojection direction.

In some embodiments, the first traces and the second traces are notcoupled to each other, and form at least one cross point in a verticalprojection direction. It should be noted that the structure in thisembodiment is a change structure of the rear section A123 of the fan-outarea A12. For example, please refer to FIG. 2 and FIG. 3, the firsttrace T11 and the second trace T21 are located on the first conductivelayer F1, the first trace T12 and the second trace T22 are located onthe second conductive layer F2. In practice, the first traces and thesecond traces are not coupled to each other. The first trace T12 and thesecond trace T2 form at least one cross point D1 which is correspondingto a projection point D1′ in a vertical projection direction. It shouldbe noted that aforementioned structure is a change structure of the rearsection A123 of the fan-out area A12 which the first traces T1 and thesecond traces T2 will leave from the fan-out area A12 and are coupled tothe multiplexer area A13. It should be noted that a length and a shapeof the traces, a length of the front section A121, the middle sectionA122, and the rear section A123 of the fan-out area A12, and a distancebetween the first conductive layer F1 and the second conductive layer F2are not limited to the embodiments shown in the figure.

In some embodiments, each of the at least three first switches of thefirst switches includes a first end, a second end, and a control end.The second ends of the at least three first switches are all connectedin parallel, and are coupled to one of the at least two first polaritypins through one of the first traces. Each of the at least three secondswitches of the second switches includes a first end, a second end, anda control end. The second ends of the at least three second switches areall connected in parallel, and are coupled to one of the at least twosecond polarity pins through one of the second traces. For example,please start from a top of components as a first end, each of threefirst switches of the first multiplexer M11 (ex. a first switch Z1, afirst switch Z2, and a first switch Z3 shown in the figure) includes thefirst end, the second end, and the control end. The second ends of thethree first switches of the first multiplexer M11 are all connected inparallel, and are coupled to the first polarity pin S11 through thefirst trace T11. The second ends of the three first switches of thefirst multiplexer M12 are all connected in parallel, and are coupled tothe first polarity pinS12 through the first trace T12.

Similarly, each of three second switches of the second multiplexer M12(ex. a second switch Z4, a second switch Z5, and a second switch Z6shown in the figure) includes a first end, a second end, and a controlend. The second ends of the three second switches of the secondmultiplexer M12 are all connected in parallel, and are coupled to thesecond polarity pin S21 through the second trace T21. The second ends ofthe three second switches of the second multiplexer M22 are allconnected in parallel, and are coupled to the second polarity pin S22through the second trace T22.

In addition, the control end of each of the first switch Z1 and thesecond switch Z4 is configured to receive a control signal from a firstsub pixel R1. The control end of each of the first switch Z2 and thesecond switch Z5 is configured to receive a control signal from a secondsub pixel G1. The control end of each of the first switch Z3 and thesecond switch Z6 is configured to receive a control signal from a thirdsub pixel B1.

In some embodiments, the first end of one of the at least three firstswitches is coupled to one of the second pixels through the first datalines. The first end of one of the at least three second switch iscoupled to one of the first pixels through the second data lines. Forexample, please refer to FIG. 2, the control ends of the first switch Z2and the second switch Z5 is configured to receive a control signal formthe second sub pixel G1, the first end of the first switch Z2 is coupledto a first data line L1 so as to control the second pixel P21, the firstend of the second switch Z5 is coupled to a second data line L2 so as tocontrol the first pixel P11. In some embodiments, one of the first datalines and one of the second data lines forms at least one cross point ina vertical projection direction. For example, the first data line L1 andthe second data line L2 are cross over to each other in the data linearea A14. In addition, the first data line L1 and he second data line L2are disposed on the different layers, and form at least one cross pointin a vertical projection direction. It should be noted that the firstdata line L1 is configured to transmit pieces of first polarity data,and the second data line L2 is configured to transmit pieces of secondpolarity data.

FIG. 4 depicts an enlarged view of a part structure diagram of a displaydevice 100A according to some embodiments of the present disclosure. Insome embodiments, compared to FIG. 2 with FIG. 4, embodiments in FIG. 4change a first number of pair of first polarity pins S1A in the bondingarea A1l and change a second number of pair of second polarity pins S2Ain the bonding area A11.

In some embodiments, the pair of first polarity pins S1 A includes atleast three first polarity pins and the pair of second polarity pins S2Aincludes at least three second polarity pins. The at least three firstpolarity pins are adjacent. The at least three second polarity pins areadjacent. The at least three first polarity pins and the at least threesecond polarity pins are arranged in an interlaced manner. The at leastthree first polarity pins are coupled to the first traces, and the atleast three second polarity pins are coupled to the second traces. Forexample, please refer to FIG. 4, a first polarity pin S11A, a firstpolarity pin S12A, and a first polarity pin S13A are adjacent. A secondpolarity pin S21A, a second polarity pin S22A, and a second polarity pinS23A are adjacent. The three first polarity pins S1A and the threesecond polarity pins S2A are arranged in the interlaced manner.

In addition, the first polarity pins S11A are coupled to the firstmultiplexer M11A through the first traces T11A. The first polarity pinsS12A are coupled to the first multiplexer M12A through the first traceT12A. The first polarity pins S13A are coupled to the first multiplexerM13A through the first trace T13A.

Similarly, the second polarity pins S21A are coupled to the secondmultiplexer M21A through the second trace T21A. The second polarity pinsS22A are coupled to the second multiplexer M22A through the second traceT22A. The second polarity pins S23A are coupled to the secondmultiplexer M23A through the second trace T23A.

In some embodiments, the fan-out area A12 further includes a thirdconductive layer. The third conductive layer is disposed on the secondconductive layer. Adjacent three first traces of the first traces aredisposed on the first conductive layer, the second conductive layer, andthe third conductive layer respectively, and are overlapped to eachother in a vertical projection direction. Adjacent three second tracesof the second traces are disposed on the first conductive layer, thesecond conductive layer, and the third conductive layer respectively,and are overlapped to each other in a vertical projection direction. Forexample, a first trace T11A, a first trace T12A, and a first trace T13Aare adjacent, are disposed on the different layers, and are overlappedto each other in a vertical projection direction. A second trace T21A, asecond trace T22A, and a second trace T23A are adjacent, are disposed onthe different layers, and are overlapped to each other in a verticalprojection direction.

In some embodiments, each of adjacent three first traces of the firsttraces is not coupled to each of adjacent three second traces of thesecond traces. For example, the first trace T11A and the second traceT21A are located on the first conductive layer. The first trace T12A andthe second trace T22A are located on the second conductive layer. Thefirst trace T13A and the second trace T23A are located on the thirdconductive layer. Each of the first traces T1A is not coupled to each ofthe second traces T2A.

FIG. 5 depicts an enlarged view of a part structure diagram of a displaydevice 100B according to some embodiments of the present disclosure. Insome embodiments, compared to FIG. 2 with FIG. 5, embodiments in FIG. 5change a third number of switches of the first multiplexers M11B in themultiplexer area A13, change a forth number of switches of the secondmultiplexers M21 B, and change the first pixels (ex. a first pixel P11Band a first pixel P12B) and the second pixels (ex. a second pixel P12Band a second pixel P22B) controlled by multiplexers. Two first pixels ofthe first pixels (ex. the first pixel P11 B and the first pixel P12B)and two second pixels of the second pixels (ex. the second pixel P12Band the second pixel P22B) are sequentially arranged as a first pixelP11 B in a first order, a second pixel P12B in a second order, a firstpixel P12B in a third order, and a second pixel P22B in a fourth order.

In some embodiments, please refer to FIG. 5, the first multiplexer M11Bincludes six switches. The six switches from top to bottom are a switchZ1 B, a switch Z2B, a switch Z3B, a switch Z4B, a switch Z5B, and aswitch Z6B. Each of the six switches includes a first end, a second end,and a control end. Please start from a top of components as a first end,each of the second end of the switch Z1B, the switch Z2B, the switchZ3B, the switch Z4B, the switch Z5B, and the switch Z6B is connected inparallel.

In addition, the second multiplexer M21 B includes six switches. The sixswitches from top to bottom are a switch Z7B, a switch Z8B, a switchZ9B, a switch Z10B, a switch Z11B, and a switch Z12B. Each of the sixswitches includes a first end, a second end, and a control end. Each ofthe second end of the switch Z7B, the switch Z8B, the switch Z9B, theswitch Z10B, the switch Z11B, and the switch Z12B is connected inparallel.

In some embodiments, each of the control end of the switch Z1 B and theswitch Z7B is configured to receive a control signal from a first subpixel R1. Each of the control end of the switch Z2B and the switch Z8Bis configured to receive a control signal from a second sub pixel G1.Each of the control end of the switch Z3B and the switch Z9B isconfigured to receive a control signal from a third sub pixel B1.

In addition, each of the control end of the switch Z4B and the switchZ10B is configured to receive a control signal from a first sub pixelR2. Each of the control end of the switch Z5B and the switch Z11B isconfigured to receive a control signal from a second sub pixel G2. Eachof the control end of the switch Z6B and the switch Z12B is configuredto receive a control signal from a third sub pixel B2.

In some embodiments, two of the six switches of the first multiplexercontrol the first pixel in the first order, one of the six switches ofthe first multiplexer controls the first pixel in the third order, oneof the six switches of the first multiplexer controls the second pixelin the second order, two of the six switches of the first multiplexercontrol the second pixel in the fourth order. In some embodiments, oneof the six switches of the second multiplexer controls the first pixelin the first order, two of the six switches of the second multiplexercontrol the first pixel in the third order, two of the six switches ofthe second multiplexer control the second pixel in the second order, oneof the six switches of the second multiplexer controls the second pixelin the fourth order. For example, the switch Z1 B and the switch Z3B ofthe first multiplexer M11B control the first pixel P11 B in the firstorder. The switch Z5B controls the second pixel P21 B in the secondorder. However, the switch Z2B the first pixel P12B in the third order.The switch Z4B and the switch Z6B control the second pixel P22B in thefourth order.

In addition, the switch Z7B and the switch Z9B of the second multiplexerM21 B control the first pixel P12B in the third order. The switch Z11Bcontrols the second pixel P22B in the fourth order. However, the switchZ8B controls the first pixel P11B in the first order. The switch Z10Band the switch Z12B control the second pixel P21 B in the second order.

In some embodiments, the peripheral area A1 shown in FIG. 1 includes theaforementioned embodiments shown in FIG. 2, or the aforementionedembodiments shown in FIG. 4, or the aforementioned embodiments shown inFIG. 5, or a combination of the aforementioned embodiments shown in FIG.2, FIG. 4, and FIG. 5.

In some embodiments, compared to a consumption of the fan-out area of aprior art, a consumption of the fan-out area A12 can be reduced by abouthalf due to a design of a two-polarity pins arrangement of theaforementioned embodiments in FIG. 2.

In some embodiments, compared to a consumption and a space height of thefan-out area of a prior art, a consumption of the fan-out area A12 canbe reduced by about two-thirds due to a design of a three-polarity pinsarrangement of the aforementioned embodiments in FIG. 2, and a spaceheight of fan-out area A12 can be reduced. It should be note that if thefan-out area A12 is located on the XY plane, the space height is along Zdirection.

In some embodiments, compared to a consumption of the fan-out area ofthree quarters due to a design of the multiplexers of the aforementionedembodiments in FIG. 5. In essence, the design is equivalent to changingthe height of the fan-out area A12. It should be note that if thefan-out area A12 is located on the XY plane, the space height is along Zdirection.

Based on the above embodiments, the present disclosure provides adisplay device so as to improve a consumption of a fan-out area of adisplay device. A design of a fan-out area of the present disclosure canreduce a space of a fan-out area for other circuit designs. The electricenergy of a display device can be used effectively due to a design of afan-out area of the present disclosure.

Although the present disclosure has been described in considerabledetail with reference to certain embodiments thereof, other embodimentsare possible. Therefore, the spirit and scope of the appended claimsshould not be limited to the description of the embodiments containedherein.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentdisclosure without departing from the scope or spirit of the presentdisclosure. In view of the foregoing, it is intended that the presentdisclosure cover modifications and variations of the present disclosureprovided they fall within the scope of the following claims.

What is claimed is:
 1. A display device, comprising: a plurality offirst pixels; a plurality of second pixels, wherein the first pixels andthe second pixels are arranged in an interlaced manner; a plurality offirst multiplexers, configured to control the first pixels, andcomprising at least three first switches, wherein one of the at leastthree first switches is configured to control the second pixels; aplurality of second multiplexers, configured to control the secondpixels, and comprising at least three second switches, wherein one ofthe at least three second switches is configured to control the firstpixels, wherein each of the first multiplexers and each of the secondmultiplexers are arranged in an interlaced manner; a plurality of firsttraces, coupled to each of the first multiplexers; a plurality of secondtraces, coupled to each of the second multiplexers; and an integratedcircuit, comprising: at least two first polarity pins, wherein the atleast two first polarity pins are adjacent; and at least two secondpolarity pins, wherein the at least two second polarity pins areadjacent, wherein the at least two first polarity pins and the at leasttwo second polarity pins are arranged in an interlaced manner, the atleast two first polarity pins are coupled to the first traces, the atleast two second polarity pins are coupled to the second traces, whereina polarity of each of the first polarity pins is opposite to a polarityof each of the second polarity pins.
 2. The display device of claim 1,wherein each of the first traces which are coupled to the at least twofirst polarity pins is adjacent, wherein each of the second traces whichare coupled to the at least two second polarity pins is adjacent.
 3. Thedisplay device of claim 2, wherein the display device comprises afan-out area, wherein the fan-out area comprises a first conductivelayer and a second conductive layer, wherein the second conductive layeris located on the first conductive layer; wherein adjacent two firsttraces of the first traces are disposed on the first conductive layerand the second conductive layer respectively, and are overlapped to eachother in a vertical projection direction; wherein adjacent two secondtraces of the second traces are disposed on the first conductive layerand the second conductive layer respectively, and are overlapped to eachother in a vertical projection direction.
 4. The display device of claim3, wherein each of the first traces is not coupled to each of the secondtraces, wherein the first traces and the second traces form at least onecross point in a vertical projection direction.
 5. The display device ofclaim 4, wherein the integrated circuit further comprises: at leastthree first polarity pins, wherein the at least three first polaritypins are adjacent; and at least three second polarity pins, wherein theat least three second polarity pins are adjacent, wherein the at leastthree first polarity pins and the at least three second polarity pinsare arranged in an interlaced manner, wherein each of the at least threefirst polarity pins is coupled the first traces, each of the at leastthree second polarity pins is coupled the second traces.
 6. The displaydevice of claim 5, wherein the fan-out area further comprises a thirdconductive layer, wherein the third conductive layer is located on thesecond conductive layer; wherein adjacent three first traces of thefirst traces are disposed on the first conductive layer, the secondconductive layer, and the third conductive layer respectively, whereinthe adjacent three first traces are overlapped to each other in avertical projection direction, wherein adjacent three second traces ofthe second traces are disposed on the first conductive layer, the secondconductive layer, and the third conductive layer respectively, whereinthe adjacent three second traces are overlapped to each other in avertical projection direction.
 7. The display device of claim 6, whereineach of the adjacent three first traces of the first traces is notcoupled to each of the adjacent three second traces of the secondtraces.
 8. The display device of claim 1, wherein each of the at leastthree first switches comprises a first end, a second end, and a controlend, wherein second ends of the at least three first switches are allconnected in parallel, and are coupled to one of the at least two firstpolarity pins through one of the first traces; wherein each of the atleast three second switches comprises a first end, a second end, and acontrol end, wherein second ends of the at least three second switchesare all connected in parallel, and are coupled to one of the at leasttwo second polarity pins through one of the second traces.
 9. Thedisplay device of claim 8, wherein the first end of one of the at leastthree first switches is coupled to the one of the second pixels througha first data line; wherein the first end of one of the at least threesecond switches is coupled to the one of the first pixels through asecond data line; wherein the first data line and the second data lineform at least one cross point in a vertical projection direction. 10.The display device of claim 1, wherein two first pixels of the firstpixels and two second pixels of the second pixels are sequentiallyarranged as a first pixel in a first order, a second pixel in a secondorder, a first pixel in a third order, and a second pixel in a fourthorder; wherein each of the first multiplexers comprises six switches,wherein two of the six switches control the first pixel in the firstorder, wherein one of the six switches controls the first pixel in thethird order, wherein one of the six switches controls the second pixelin the second order, wherein two of the six switches control the secondpixel in the fourth order; wherein each of the second multiplexerscomprises six switches, wherein one of the six switches controls thefirst pixel in the first order, wherein two of the six switches controlthe first pixel in the third order, wherein two of the six switchescontrol the second pixel in the second order, wherein one of the sixswitches controls the second pixel in the fourth order.